Robotic Wafer Bumping Line engineered by APSTL at a US customer 

Low cost Pb - free Solder Capped Column Bump for Wafer Level Packaging developed by APSTL

for details contact 

Dr. D. Gupta

Chief Technical Officer

APSTL llc

Scottsdale. AZ, USA

e-mail : dgupta@apstl.com

phone : (480) 518-4570

For the User of Advanced Packaging technologies

Advanced Packaging is now recognized by the Designers of Electronic Systems as a key enabling technology, especially for the lucrative but very competitive Portable Systems segment. But access to even state of the art Packaging technologies such as Flip Chip and Wafer Level Packaging originally developed in the US are now channeled through large Assembly houses based in the Far East. To select and use these overseas providers of Advanced Packaging technologies, prospective users can benefit from both technical as well as logistical assistance by experts.

With our deep expertise in the technical aspects of Advanced Packaging, as well as experience in managing Technology Development at overseas Suppliers for High Density Organic substrates, we believe that APSTL is uniquely qualified to assist you for your next Project.

Be it just a quick failure and root cause analyses for your current packages or all the way to the development of reliable interconnect and packaging technologies for your custom applications and then putting the into production, you can depend on the proven track record of APSTL 

Based on our success in developing many of the key Packagiing technologies that have now become industry standards and implementing them at semiconductor companies both large ( such as Motorola and Intel ) and small,  we are confident that we can satisfy your needs.